1. Technical Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a manufacturing method of the same, and in particular, to a technology to be effectively applied to a semiconductor integrated circuit device (Bipolar Complementary Metal Oxide Semiconductor LSI to be simply referred to as bipolar CMOS LSI herebelow) including bipolar transistors and MISFETs on a substrate thereof.
2. Description of the Prior Art
Conventionally, a bipolar CMOS LSI is described, for example, in the Digest of Technical Papers of IEDM 1985, pp. 423-426.
In this bipolar CMOS LSI, on an epitaxial layer formed on a semiconductor substrate, there is arranged a thick field insulation layer for separating device elements according to the known selective oxidation method, thereby providing an area for disposing a bipolar transistor and an area for arranging a MISFET. On surfaces of activation areas enclosed with the field insulation layer, there is formed a thin insulation film. Thereafter, a first polycrystalline silicon layer is formed on the entire surface of the semiconductor substrate and is then a patterning operation is achieved thereon so as to dispose gate electrodes of the MISFETs in predetermined areas, and next, an ion bombardment to implant a p-type impurity substance is effected to form base regions of the bipolar transistors. Subsequently, source and drain regions of the n-channel and p-channel MISFETs are established by the ion bombardment of n-type and p-type impurity substances, respectively. In the impurity ion bombardment to dispose the source and drain regions of the p-channel MISFETs, graft base regions of the bipolar transistors are also formed by use of a predetermined mask. Thereafter, in order to provide emitter regions of the bipolar transistors, portions of the thin insulation film are removed through an etching operation and then a second polycrystalline silicon layer is disposed on the entire surface of the semiconductor substrate. Subsequently, for example, arsenic is doped into the second polycrystalline silicon layer, which then undergoes a patterning such that only portions corresponding to the emitter regions to be disposed are remained. Thereafter, an annealing operation is effected in the state above, which causes the arsenic in the second polycrystalline silicon layer to be diffused into the epitaxial layer, thereby establishing the emitter regions in the base regions. The polycrystalline silicon layer in the emitter regions is kept so as to be used as emitter electrodes. Next, an insulation layer is formed for passivation on the overall surface of the semiconductor substrate, contact holes are established in the insulation layer, and an aluminum film is applied on the entire surface. Thereafter, the aluminum film undergoes a patterning so as to form aluminum electrodes for the emitters, bases, and collectors of the bipolar transistors and aluminum electrodes for the source and drain regions of the MISFETs.